It is known to monitor a set of one or more digital signals produced by digital signal processors, microcontrollers, logic analyzers and other circuits for the occurrence of any of several predetermined conditions, i.e. combination of signal values, in the set. In the case of logic analyzers, manufacturers normally include a trace buffer memory in the device for simply recording the signal states for some specified set of signals over the most recent clock cycles, thereby providing a trace history that can be later analyzed if some problem occurs. The size of the buffer determines the exact number of recent cycles that can be stored, and generally, no real-time notification of any predefined condition in the monitored signals is given. In the case of some other circuits, such as digital signal processors (DSP), it is common to generate a breakpoint (or halt) signal in response to the detection of a predefined condition in a set of signals being monitored by a breakpoint unit. The operation of the DSP, microcontroller, or other circuit is then immediately halted in the same clock cycle, so that a programmer or other user can analyze the internal state of the circuit, including for example the values contained in the various registers of the circuit, in an effort to identify the programming or other error that caused the condition to occur. One example of a specific condition of interest to be monitored for is an attempt to access a memory at an address that is outside a predetermined range. In microcontrollers, DSPs and the like, a start-up or bootstrap routine is usually executed when power is first turned on to preset registers and other circuit elements to a desired initial state. The breakpoint unit can monitor signals during the routine for certain signal states that indicate that the start-up cycle is complete. A "breakpoint" signal generated by the unit may then initiate normal operation of the circuit.
Conventional breakpoint units use dedicated comparator circuits, each operating on the set of signals being observed to detect the occurrence of some condition for those signals and to output an indication of any such detected occurrence. An example of such a breakpoint unit with two comparators is illustrated in FIG. 1. Each comparator is dedicated to detecting a different signal condition, and in practice there may be as many as 16 comparators in a breakpoint unit for detecting a like number of conditions. In FIG. 1, the breakpoint unit includes a first comparator 2, a second comparator 4 and an inclusive OR gate 6. The comparators 2 and 4 receive as inputs a set of signals B.sub.1, B.sub.2, . . . , B.sub.N to be monitored. These signals may represent, for example, attempts by a digital signal processor, microcontroller, logic analyzer or other circuit to access instructions from a program memory or to access data to or from one or more data memories at certain addresses, or may represent other outputs from or inputs to these circuits. Thus, the comparator inputs may represent memory addresses, data, error flags (such as overflow) and other signals. While FIG. 1 shows both comparators 2 and 4 receiving the same signals B.sub.1, B.sub.2, . . . , B.sub.N, different comparators might receive and thereby monitor different or overlapping sets of signals. The first comparator 2 receives, or has stored internally, a set of reference signals R.sub.1, R.sub.2, . . . , R.sub.N equal in number and corresponding to the signals B.sub.1, B.sub.2, . . . , B.sub.N being monitored. The reference signals R.sub.1, R.sub.2, . . . , R.sub.N represent the signal values for the condition to be detected. When each of the input signals B.sub.i (i=1 to N) matches its corresponding reference signal R.sub.i, the comparator 2 outputs an indication signal I.sub.i with a logic level "1" representing an occurrence of the condition being sought in the input signals B.sub.1, B.sub.2, . . . , B.sub.N being monitored. Otherwise, the comparator 2 outputs a logic level "0" for the indication signal I.sub.1. Similarly, the second comparator 4 receives, or has stored internally, a different set of reference signals R.sub.1 ', R.sub.2 ', . . . , R.sub.N ', representing a different condition for the input signals B.sub.1, B.sub.2, . . . , B.sub.N being monitored. The comparator 4 outputs a second indication signal I.sub.2, which is a logic level "1" if the condition is detected and a logic level "0" whenever the condition is not detected.
The results of the comparisons may be individually used, as shown for first indication signal I.sub.1. For example, one indication signal may signal a desired starting condition, while some other indication signal may signal a desired stopping condition. Alternatively, two or more indication signals may be combined in some logical fashion by one ore more logic gates. For example, in FIG. 1, the first and second indication signals I.sub.1 and I.sub.2 output by the comparators 2 and 4 are input into an inclusive-OR gate 6. A third indication I.sub.3 is output by the gate 6 and indicates the occurrence of either condition of interest.
A typical comparator 8 is implemented as shown in FIG. 2. The comparator includes a set of exclusive-NOR (XNOR) or exclusive-OR gates 10.sub.1, 10.sub.2, . . . , 10.sub.N, one for each of the N input signals B.sub.1, B.sub.2, . . . , B.sub.N to be monitored and compared with reference values R.sub.1, R.sub.2, . . . , R.sub.N. The reference values R.sub.1, R.sub.2, . . . , R.sub.N may be stored in an N-Bit register 12. Thus, each XNOR logic gate 10.sub.1, 10.sub.2, . . . , 10.sub.N receives two inputs, one an input signal B.sub.i (i=1 to N) and the other a corresponding reference signal R.sub.i. Each gate outputs the result of its bit-comparison. The comparator also includes a set of (N-1) two-input AND gates 14.sub.1, 14.sub.2, . . . , 14.sub.N-1. (An N-input AND gate could be used in their place if N is not too large.) The result of combining all N bit-comparison results is output as the indication signal I.sub.j for this j-th comparator 8 of the breakpoint unit. This implementation normally limits comparisons to 8-bit input signals, or in extreme cases possibly to 16-bit input signals. Further, each comparator is usually implemented on a separate integrated circuit chip.
Prior breakpoint units are limited in practice to a small number of user definable conditions, since the conventional approach allows only a single match condition for each dedicated comparator device. Thus prior units only allow a user to detect and act upon a small number of simple conditions of interest. With 16 comparators, for example, a breakpoint unit is capable of monitoring a DSP's access to eight program memory addresses, four data memory addresses and four data values (i.e., accessed memory contents). Complicated logical combinations of several operating conditions are prohibitively expensive, so only simple combinations are attempted. For example, one possible combination for conventional units is: IF ANY OF ADDRESS EQUALS 42 OR ADDRESS EQUALS 85 OR DATA EQUALS 22 OR DATA EQUALS 27, THEN STOP. Further, even with these limited monitoring capabilities, the comparator/logic circuit requirements generally dictate an off-chip breakpoint unit separate from the device being monitored.
An objective of the present invention is to provide apparatus capable of monitoring sets of signals for an arbitrarily large number of defined conditions or condition classes and to providing real-time notification for beginning or halting operation of a circuit upon detection of the occurrence of any one or more of those conditions in a monitored signal set or sets.
Another objective of the present invention is to provide an efficient way of providing the above-mentioned notification for logical combinations of defined signal conditions.
Yet another objective of the present invention is to provide the above-mentioned apparatus in which the defined conditions can be readily reprogrammed.